(A) Field of the Invention
The present invention relates to a method for preparing a deep trench and an etching mixture for the same, and more particularly, to a method for preparing a deep trench of a DRAM cell and an etching mixture for the same.
(B) Description of the Related Art
A memory cell of the DRAM consists of a metal oxide field-effect transistor and a capacitor on the silicon substrate, and the source of the transistor is electrically connected to the upper storage plate of the capacitor. There are two types of capacitors: stack and deep trench. The stack capacitor is fabricated directly on the surface of the silicon substrate, while the deep trench capacitor is fabricated inside the silicon substrate. Recently, the integrity of the DRAM has increased with the innovation of semiconductor process technology rapidly. However, the size of the memory cell must be shrunk to achieve the purpose of high integrity, i.e., increasing the integrity needs to reduce the size of the transistor and the capacitor.
FIG. 1 is a cross-sectional diagram of a deep trench 10 according to the prior art. As shown in FIG. 1, the method for preparing the deep trench 10 first forms a hard mask layer 14 and a photoresist layer 16 on a silicon substrate 12, and a photolithography process is then performed to form two openings 18 in the photoresist layer 16. An anisotropic etching process, such as the reactive ion etching process or the plasma etching process, is performed to remove a portion of the hard mask layer 14 and silicon substrate 12 under the two openings 18 to form two deep trenches 10 in the silicon substrate 12. As the diameter of the deep trench 10 shrinks, the deep trench 10 deviates from being the same diameter, but tends to have a larger diameter at the upper portion and a smaller diameter at the bottom portion.
The capacitance is proportional to the surface area of the electrode, and the surface area of the electrode for the deep trench capacitor is a product of the depth and the circumference of the deep trench, wherein the circum area depends on the diameter of deep trench. With the continuous reduction of the DRAM cell, the diameter of the deep trench is reduced accordingly, and the deep trench 10 cannot provide a sufficient surface area according to the prior art. In addition, with the continuous reduction of the DRAM cell, the width of a local silicon substrate 20 separating the two deep trenches 10 becomes smaller. Consequently, the local silicon substrate 20 may be removed during the subsequent etching process to result in the direct connecting of the two deep trenches 10, which invalidate the subsequent formed capacitor due to electrical connecting.